FIG. 8 of the attached drawings is a circuit view of, for example, a conventional discharge-processing power-source assembly. In FIG. 8, the reference numeral 10 denotes a D.C. power source; 12, a workpiece; 13, an electrode; and 14a, 14b, a first pair of switching elements which, here, are power MOS-FETs; 16a and 16b, a second pair of switching elements which, here, are power MOS-FETs; 15a, 15b, 15c, 15d, snubber circuits for protecting the power MOS-FETs 14a and 14b, and 16a and 16b, each of which is composed of a diode, a capacitor, and a resistance. The reference numeral 17 denotes a discharge preventing resistance.
Operation will next be described. D.C. voltage is applied to a location between the processing electrode 13 and the workpiece 12 (hereinafter referred to as "an interpole location") by the D.C. power source 10, and the first pair of switching elements 14a and 14b are turned ON/OFF simultaneously for a predetermined period of time, to generate a group of pulses of positive voltage, thereby executing discharge processing. Subsequently, the second pair of switching elements 16a and 16b are turned ON/OFF simultaneously for a predetermined period of time, to generate a group of pulses of reverse voltage. However, in order to make it difficult to generate discharge, the discharge preventing resistance 17 is inserted as shown in FIG. 8. This series of operations is executed repeatedly so that discharge processing proceeds.
A waveform of the interpole discharge voltage will next be described with reference to FIGS. 9(a) and 9(b). FIG. 9(a) shows a waveform of the interpole discharge voltage at the time a switching frequency is low (equal to or less than several tens (10) KHz). However, discharge is surely or certainly executed one by one. When the switching elements are turned OFF, the interpole voltage is brought to 0 V. On the other hand, the waveform of the interpole discharge voltage at the time the switching frequency is high (equal to or more than several hundreds (100) KHz) is illustrated in FIG. 9(b). However, once discharge occurs, even if the switching elements are turned OFF, an impedance of the snubber circuits is lowered because the frequency is high, so that processing current does not pass through the switching elements, but continues to flow through the diodes and capacitors of the snubber circuits, as seen for I.sub.1 (on the side of positive voltage) and I.sub.2 (on the side of reverse voltage) illustrated in FIG. 8). Thus, the processing current is brought to concentrated discharge, and the waveform of the interpole discharge voltage is not brought to 0 V even if the switching elements are turned OFF, but is brought to arc voltage.
Further, FIG. 10 is a circuit view of another conventional discharge-processing power-source assembly. In FIG. 10, the reference numeral 20 denotes a first D.C. power source; 22, a workpiece; 23, a wire electrode; 24a, 24b, a first pair of switching elements which, here, are power MOS-FETs; 25a, 25b, 25c, 25d, diodes for protecting the power MOS-FETs; 26a, 26b, a second pair of switching elements which, here, are power MOS-FETs; 27a, 27b, 27c, 27d, diodes for protecting the power MOS-FETs; 28, a current limiting resistance for positive voltage; 29, a current limiting resistance for reverse voltage; 50, a second D.C. power source; 51, a third switching element which, here, is a power MOS-FET; and 52, a surge absorbing circuit.
Operation will next be described. D.C. voltage is applied to the interpole location between the processing electrode 23 and the workpiece 22 by the first D.C. power source 20, and the first pair of switching elements 24a and 24b are simultaneously turned ON, to generate discharge through the current limiting resistance 28 for positive voltage. Immediately thereafter, the third switching element 51 is turned ON so that processing current contributing to processing treatment flows between poles due to the second D.C. power source 50. After a predetermined on-time has been completed, the first pair of switching elements 24a and 24b and the third switching element 51 are turned OFF. Subsequently, the second pair of switching elements 26a and 26b are simultaneously turned ON, to apply reverse voltage to the interpole location through the current limiting resistance 29 for reverse voltage. This series of operations is executed repeatedly so that discharge-processing treatment proceeds. The operation waveform is illustrated in FIG. 11.
In FIG. 11, the first pair of switching elements 24a and 24b are set to ON state, as illustrated at waveform A step (1). At this point, the second and third switching elements 26a, 26b and 51 are in OFF state. Next, voltage (V.sub.0) is applied to the interpole location from the first D.C. power source 20, as seen in waveform D of FIG. 11 at step (2). If a dielectric breakdown occurs at the interpole location, the voltage is dropped from voltage V.sub.0 to an arcing voltage, as seen in waveform D at step (3).
After a dielectric breakdown has occurred, the third switching element 51 is set to an ON state at once, as seen at step (4) of waveform B, for a fixed time t. Meanwhile, the first pair of switching elements 24a and 24b remain in an ON state (overlap state) at the same time, as seen in waveform A. Thereafter, the first pair of switching elements 24a and 24b are set to an OFF state, as seen in waveform A at step (5). It should be noted that after the third switching element 51 is set to ON state at step (4), and processing current is applied to the interpole location from the second D.C. power source 50, as seen in waveform E.
The slope of the processing current at step (7) of waveform E is decided by the inductance (L) of the feeder connected to the interpole location from the second D.C. power source 50. This relationship is represented by the following expression: ##EQU1## I: processing current V: second D.C. power source voltage
L: inductance of feeder PA1 t: On time of third switching element
After desired ON time (t) is passed, the third switching element 51 is set to an OFF state, as seen in waveform B at step (8). Thereafter, the processing current does not change to zero at once, even through the third switching element 51 is set to an OFF state, and the processing current continue to flow until an energy stored in inductance of the feeder changes to zero. This current route is shown by I.sub.1 and I.sub.2 in FIG. 10 and is illustrated in waveform E at step (9).
When the processing current (waveform E) and arcing voltage (waveform D) at the interpole location are changed to zero (step 10), the second pair of switching elements 26a and 26b are set to an ON state at once, as seen at step (11) of waveform C. As a result, reversed polarity voltage is applied to the interpole location from the first D.C. power source 20 and waveform D falls to step (12). After fixed time is passed, the second pair of switching elements 26a and 26b are set to the OFF state, and the voltage value at the interpole location is changed to zero, as seen at step (13).
The above steps (1)-(13) comprise one cycle for one processing. While the processing is being executed for one cycle, when the third switching element 51 is set to the OFF state, as seen in step (8) of waveform B, the current (I.sub.2) continues to flow to the first D.C. power source 20, as seen at step (9) of waveform E. Since a capacitor (not shown) is connected to the first D.C. power source 20, the current continues to flow to the capacitor. Accordingly, an output voltage of the first D.C. power source 20 rises from V.sub.0 to V.sub.0 ', as seen in waveform D, and breakage of the wire occurs.
FIG. 12 is a circuit view of another conventional discharge-processing power-source assembly. In FIG. 12, the reference numeral 30 denotes a D.C. power source; 32, a workpiece; 33, an electrode; 34a, 34b, a first pair of switching elements which, here, are power MOS-FETs; 36a, 36b, a second pair of switching elements which, here, are power MOS-FETs; 35a, 35b, 35c and 35d, diodes for protecting the power MOS-FETs; and 37, a current limiting resistance.
Operation will next be described. D.C. voltage is applied to the interpole location between the processing electrode 33 and the workpiece 32, and the first pair of switching elements 34a and 34b are simultaneously turned ON/OFF for a predetermined period of time, to generate a pulse of positive voltage for executing discharge processing. Subsequently, the
second pair of switching elements 36a and 36b are simultaneously turned ON/OFF for a predetermined period of time, to generate a pulse of reverse voltage. The current limiting resistance 37 is inserted in order to obtain a desired discharge current. This series of operations is repeatedly executed so that discharge processing treatment proceeds.
Here, in order that upper and lower switching elements in a first arm (a portion comprising an upper side of the first pair of switching elements and a lower side of the second pair of switching elements together) or a second arm (a portion comprising a lower side of the first pair of switching elements and an upper side of the second pair of switching elements together) do not cause short-circuiting, it is necessary that both the first/second pairs of switching elements are brought to an OFF condition (dead time) when there is switching between a positive voltage and a reverse voltage (t1 period illustrated in FIG. 13). The dead time prevents two pulses from overlapping and causing a short circuit.
Ordinarily, high processing speed is desired and the discharge frequency must be raised in order to increase the processing speed. For this purpose, it is required that the dead time is shortened and brought close to 0. However, even if the dead time is shortened so as to be located in the neighborhood of 0, the dead time may be insufficient to prevent a short circuit of these are completely runs out by variations in the electronic circuit parts for generating the dead time, variations in the characteristic of the electronic parts attendant upon variation in disturbance due to a temperature and the like, and further by malfunction due to noises or the like. Thus, upper and lower or vertical short-circuiting may be caused by the operation of the concurrent first/second arms.
As reference technical literatures relating the patent invention, there are "ELECTRIC POWER-SOUSE ASSEMBLY FOR DISCHARGE-PROCESSING DEVICE" disclosed in Japanese Patent Laid-Open No.SHO 63-221919, and "ELECTRIC POWER-SOUSE ASSEMBLY FOR DISCHARGE-PROCESSING" disclosed in Japanese Patent Laid-Open No.HEI 2-71920.
The conventional discharge-processing power-source assembly has been constructed as described above. Accordingly, once discharge occurs, discharge current continues to flow through the snubber circuits, even if the switching elements are turned OFF (this particularly noticeably appears if the switching frequency is high). Thus, there is a problem that concentrated discharge occurs so that a processed surface is roughened, or breakage of a wire occurs.
Further, for the conventional discharge-processing power-source assembly that has been constructed as described above, the surge current flowing at the time the third switching element is turned OFF is regenerated also at the first D.C. power source (I.sub.2 illustrated in FIG. 10), in addition to the surge absorbing circuit (I.sub.1 illustrated in FIG. 10). Open voltage V.sub.0 at the time discharge is first generated rises. Thus, there is a problem that breakage of the wire occurs.
Furthermore, for the conventional discharge-processing power-source assembly that has been constructed for high speed processing as described above, the dead time completely runs out, and there is a case where vertical short-circuiting occurs at the first/second arms. When excessive current flows through the switching elements (I.sub.1 and I.sub.2 illustrated in FIG. 12), there is a problem that the switching elements are destroyed so that processing treatment is disabled.